The present invention relates to digital signal processing, and more particularly to resembling to adjust sampling rates.
Various consumer products use digital signals, such as music on CDs, images in digital cameras, and video on DVDs, and multiple sampling rates have been used create the digital files. The playout/display device for such a digital file may require a sampling rate differing from that of the digital file to be played, and thus resembling to adjust the sampling rate is needed. For example, music may be sampled at 16 KHz, 44.1 KHz, or 48 KHz, and images at 1600×1200 pixels or 640×480 pixels. The resembling factor is the ratio of the new sampling rate divided by the original sampling rate.
It is generally easier to implement resembling when the resembling factor is either an integer (upsampling) or the reciprocal of an integer (downsampling). Fractional resembling (resembling factor is U/D where U and D are integers greater than 1) is more complicated to implement but frequently required in real applications. For example, the digital zoom feature of camcorders and digital cameras often involves a series of finely-spaced zoom factors such as 1.1×, 1.2×, 1.3×, and so on.
Crochiere et al, Multirate Digital Signal Processing (Prentice-Hall 1983) includes resembling theory and structures. In particular, FIG. 2a shows generic resembling (a rate converter) which first expands the sampling rate by a factor of U, lowpass filters to eliminate aliasing, and then compresses the sampling rate by a factor of D. The sampling rate expansion is just inserting 0s, and the sampling rate compression is just discarding samples. The lowpass filter leads to computational complexity, and a polyphase filter implementation as illustrated in FIG. 2b helps avoid unnecessary multiplications and additions. However, such a polyphase filter implementation inherently requires irregular data access in the sense that input/output addressing involves fractional arithmetic.
Generally, single-thread, VLIW (very long instruction word), SIMD (single instruction, multiple dispatch), and vector DSP processor architectures have a high level of efficiency for multiply-accumulate (MAC) operations with regular data access in the sense of simple, well-behaved, multi-dimensional addressing. In a conventional single-thread DSP, simple and regular data access is sometimes free but otherwise requires little computation time. In a VLIW DSP, simple and regular data access can execute simultaneously with MAC instructions, and thus is often free. A SIMD DSP often requires that the data be organized sequentially to align with the wide memory/register word, so simple and regular access is mandatory in order to take advantage of the SIMD features. A vector DSP usually has hardware address generation and loop control, and these hardware resources cannot deal with anything but simple and regular addressing. Straightforward implementation of fractional resembling on various digital signal processor architectures is thus fairly inefficient.
Thus there is a problem to adapt polyphase filter resembling methods for efficient operation on DSPs.